Video processing circuit with line memory control

ABSTRACT

A line memory and control system comprises a line memory, for example a first in first out (FIFO) device. A comparator compares a first value, specifying a location in the horizontal line period where reading or writing of the line memory is to begin, with a second value, fixing pixel location within each line period. A register stores the number of data samples stored in the line memory. A counter counts the number of data samples which have actually been written into the line memory or read from the line memory. The counter has an output of the comparator as a first input and the number of data samples previously stored in the line memory as a second input. In the case of both compression and expansion, a line memory control system assures that the number of samples written into each FIFO line memory be the same as the number of samples read out of each FIFO line memory.

BACKGROUND OF THE INVENTION

The invention relates to the field of televisions, for example thosetelevisions having a wide display format ratio screen, which mustinterpolate video data to implement various display formats. Mosttelevisions today have a format display ratio, horizontal width tovertical height, of 4:3. A wide format display ratio corresponds moreclosely to the display format ratio of movies, for example 16:9. Theinvention is applicable to both direct view televisions and projectiontelevisions.

Televisions having a format display ratio of 4:3, often referred to as4×3, are limited in the ways that single and multiple video signalsources can be displayed. Television signal transmissions of commercialbroadcasters, except for experimental material, are broadcast with a 4×3format display ratio. Many viewers find the 4×3 display format lesspleasing than the wider format display ratio associated with the movies.Televisions with a wide format display ratio provide not only a morepleasing display, but are capable of displaying wide display formatsignal sources in a corresponding wide display format. Movies "look"like movies, not cropped or distorted versions thereof. The video sourceneed not be cropped, either when converted from film to video, forexample with a telecine device, or by processors in the television.

Televisions with a wide display format ratio are also suited to a widevariety of displays for both conventional and wide display formatsignals, as well as combinations thereof in multiple picture displays.However, the use of a wide display ratio screen entails numerousproblems. Changing the display format ratios of multiple signal sources,developing consistent timing signals from asynchronous butsimultaneously displayed sources, switching between multiple sources togenerate multiple picture displays, and providing high resolutionpictures from compressed data signals are general categories of suchproblems. Such problems are solved in a wide screen television accordingto this invention. A wide screen television according to variousinventive arrangements is capable of providing high resolution, singleand multiple picture displays, from single and multiple sources havingsimilar or different format ratios, and with selectable display formatratios.

Televisions with a wide display format ratio can be implemented intelevision systems displaying video signals both at basic or standardhorizontal scanning rates and multiples thereof, as well as by bothinterlaced and noninterlaced scanning. Standard NTSC video signals, forexample, are displayed by interlacing the successive fields of eachvideo frame, each field being generated by a raster scanning operationat a basic or standard horizontal scanning rate of approximately 15,734Hz. The basic scanning rate for video signals is variously referred toas f_(H), 1f_(H), and 1H. The actual frequency of a 1f_(H) signal willvary according to different video standards. In accordance with effortsto improve the picture quality of television apparatus, systems havebeen developed for displaying video signals progressively, in anoninterlaced fashion. Progressive scanning requires that each displayedframe must be scanned in the same time period allotted for scanning oneof the two fields of the interlaced format. Flicker free AA-BB displaysrequire that each field be scanned twice, consecutively. In each case,the horizontal scanning frequency must be twice that of the standardhorizontal frequency. The scanning rate for such progressively scannedor flicker free displays is variously referred to as 2f_(H) and 2H. A2f_(H) scanning frequency according to standards in the United States,for example, is approximately 31,468 Hz.

Considerable signal processing of the main video signal is necessary toimplement many of the display formats which are especially appropriatefor a wide screen television. The video data must be selectivelycompressed and expanded, depending upon the desired format. In one case,for example, it is necessary to compress the 4×3 NTSC video by a factorof 4/3 to avoid aspect ratio distortion of the displayed picture. In theother case, for example, the video can be expanded to perform horizontalzooming operations usually accompanied by vertical zooming. Horizontalzoom operations up to 33% can be accomplished by reducing compressionsto less than 4/3. A sample interpolator is used to recalculate theincoming video to a new pixel positions because the luminance videobandwidth, up to 5.5 MHz for S-VHS format, occupies a large percentageof the Nyquist fold over frequency, which is 8 MHz for a 1024f_(H)system clock.

The luminance data for the main signal is routed along a main signalpath including a FIFO line memory for compressing and expanding the dataand an interpolator for recalculating sample values, based on thecompression or the expansion of the video, to smooth the data. However,the relative positions of the FIFO and the interpolator are differentfor compression than for expansion. In accordance with an inventivearrangement, switches or route selectors reverse the topology of themain signal path with respect to the relative positions of the FIFO andthe interpolator, avoiding the need for two main signal paths requiringtwo FIFOs and two interpolators. In particular, these switches selectwhether the interpolator precedes the FIFO, as required for compression,or whether the FIFO precedes the interpolator, as required forexpansion. The switches can be responsive to a route control circuitwhich is itself responsive to a microprocessor.

An interpolator control circuit generates pixel position values,interpolator compensation filter weighting and clock gating informationfor the luminance data. It is the clock gating information whichdecimates or repeats the FIFO data to allow more samples to be writtenthan read for effecting compression or more samples to be read thanwritten for expansion. In order to process a 4/3 compression, forexample, every fourth sample can be inhibited from being written intothe FIFO. The average slope of a ramp read out of the luminance FIFO is33% steeper than the corresponding input ramp. Note also that 33% lessactive reading time is required to read out the ramp as was required towrite in the data. This constitutes the 4/3 compression. It is thefunction of the interpolator to recalculate the luminance samples beingwritten into the FIFO so that the data read out of the FIFO is smooth,rather than jagged.

Expansions may be performed in exactly the opposite manner ascompressions. In the case of compressions the write enable signal hasclock gating information attached to it in the form of inhibit pulses.For expanding data, the clock gating information is applied to the readenable signal. This will pause the data as it is being read from theFIFO. The average slope of a ramp read out of the luminance FIFO is 33%more shallow than the corresponding input ramp for a 4/3 expansion orzoom. In this case it is the function of the interpolator, which followsthe FIFO, to recalculate the sampled data from jagged to smooth afterthe expansion. In the expansion case the data must pause while beingread from the FIFO and while being clocked into the interpolator. Thisis different from the compression case where the data is continuouslyclocked through the interpolator. For both cases, compression andexpansion, the clock gating operations can easily be performed in asynchronous manner, that is, events can occur based on the rising edgesof the 1024f_(H) system clock.

There are a number of advantages in this topology for luminanceinterpolation. The clock gating operations, namely data decimation anddata repetition, may be performed in a synchronous manner. If aswitchable video data topology were not used to interchange thepositions of the interpolator and FIFO, the read or write clocks wouldneed to be double clocked to pause or repeat the data. The term doubleclocked means that two data points must be written into the FIFO in asingle clock cycle or read from the FIFO during a single clock cycle.The resulting circuitry cannot be made to operate synchronously with thesystem clock, since the writing or reading clock frequency must be twiceas high as the system clock frequency. Moreover, the switchable topologyrequires only one interpolator and one FIFO to perform both compressionsand expansions. If the video switching arrangement described herein werenot used, the double clocking situation can be avoided only by using twoFIFO's to accomplish both compression and expansion. One FIFO forexpansions would need to be placed in front of the interpolator and oneFIFO for compressions would need to be placed after the interpolator.

SUMMARY OF THE INVENTION

One of the conditions for proper circuit operation is that the number ofdata samples written into the FIFO for each horizontal line be exactlyequal to the number of samples read from the FIFO for that horizontalline. If the same number of samples are not written into the FIFO as areread out of the FIFO, then the main channel picture will be severelyslanted due to line by line pointer precession, read or write. Thisrequirement is dictated by the fact that the main channel FIFOs arereset once per field. First the write pointer is reset following a mainsignal vertical synchronizing pulse and then one line later the readpointer is reset.

A different number of clock cycles may be required for the read andwrite pointers to advance to the same number of places due to the factthat expansions and compressions of video data are taking place. Inorder for the number of data samples written to always equal the numberof data samples read, regardless of mode, three register values and twocontrol signals are used to generate the read and write enables for themain Y and UV FIFOs. Two register values WR₋₋ BEG₋₋ MN and RD₋₋ BEG₋₋MN, provided by a microprocessor, specify the location in the horizontalline period where reading and writing are to begin, in conjunction witha horizontal pixel count value H₋₋ COUNT. The value H₋₋ COUNT is a tenbit counter value used to determine pixel location within the lineperiod. The counter is cleared by a start of line signal SOL. The SOLsignal is a single clock wide pulse used to initialize the horizontalcounter H₋₋ COUNT to a value of zero at the beginning of every line. TheSOL pulse is nominally aligned with the leading edge of the horizontalsynchronizing component.

A third register value LENGTH is used to load the upper eight bits of aten bit counter to determine the number of data samples which haveactually been written into the FIFO or read from the FIFO. The bits ofthe register value are inverter, and the least significant two bits areloaded logically HI, resulting in ₋₋ LENGTH-1. A ₋₋ preceding a signaldenotes a logical inversion. Accordingly, when the counter overflows,that is the ripple carry out goes HI, the desired number of samples willhave been written, or read. The actual number of pixel samples written,or read, is actually LENGTH×4 because the register is loaded into theupper eight bits of the counter. The effect of the clock gating isaccounted for by gating the counter enable. In this way, the enable forthe counter may also be used as the enable for the FIFO, ensuring thatthe number of samples written, or read, is always LENGTH×4, regardlessof mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a)-1(i) are useful for explaining different display formats of awide screen television.

FIG. 2 is a block diagram of a wide screen television in accordance withaspects of this invention and adapted for operation at 2f_(H) horizontalscanning.

FIG. 3 is a block diagram of the wide screen processor shown in FIG. 2.

FIG. 4 is a block diagram showing further details of the wide screenprocessor shown in FIG. 3.

FIG. 5 is a block diagram of the picture-in-picture processor shown inFIG. 4.

FIG. 6 is a block diagram of the gate array shown in FIG. 4 andillustrating the main, auxiliary and output signal paths.

FIGS. 7 and 8 are timing diagrams useful for explaining the generationof the display format shown in FIG. 1(d), using fully cropped signals.

FIG. 9 is a block diagram showing the main signal path of FIG. 6 in moredetail.

FIG. 10 is a block diagram showing the auxiliary signal path of FIG. 6in more detail.

FIG. 11 is a block diagram of the timing and control section of thepicture-in-picture processor of FIG. 5.

FIG. 12 is a block diagram of a circuit for generating the internal2f_(H) signal in the 1f_(H) to 2f_(H) conversion.

FIG. 13 is a combination block and circuit diagram for the deflectioncircuit shown in FIG. 2.

FIG. 14 is a block diagram of the RGB interface shown in FIG. 2.

FIG. 15 illustrates waveforms useful for explaining video compression.

FIG. 16 illustrates waveforms useful for explaining video expansion.

FIG. 17 is a block diagram of a line memory control circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The various parts of FIG. 1 illustrate some, but not all of the variouscombinations of single and multiple picture display formats which can beimplemented according to different inventive arrangements. Thoseselected for illustration are intended to facilitate the description ofparticular circuits comprising wide screen televisions according to theinventive arrangements. The inventive arrangements are in some casesdirected to the display formats themselves, apart from specificunderlying circuitry. For purposes of convenience in illustration anddiscussion herein, a conventional display format ratio of width toheight for a video source or signal is generally deemed to be 4×3,whereas a wide screen display format ratio of width to height for avideo source or signal is generally deemed to be 16×9. The inventivearrangements are not limited by these definitions.

FIG. 1(a) illustrates a television, direct view or projection, having aconventional format display ratio of 4×3. When a 16×9 format displayratio picture is transmitted, as a 4×3 format display ratio signal,black bars appear at the top and at the bottom. This is commonlyreferred to as letterbox format. In this instance, the viewed picture israther small with respect to the entire available display area.Alternatively, the 16×9 format display ratio source is converted priorto transmission, so that it will fill the vertical extent of a viewingsurface of 4×3 format display. However, much information will be croppedfrom the left and/or right sides. As a further alternative, theletterbox picture can be expanded vertically but not horizontally,whereby the resulting picture will evidence distortion by verticalelongation. None of the three alternatives is particularly appealing.

FIG. 1(b) shows a 16×9 screen. A 16×9 format display ratio video sourcewould be fully displayed, without cropping and without distortion. A16×9 format display ratio letterbox picture, which is itself in a 4×3format display ratio signal, can be progressively scanned by linedoubling or line addition, so as to provide a larger display withsufficient vertical resolution. A wide screen television in accordancewith this invention can display such a 16×9 format display ratio signalwhether the main source, the auxiliary source or an external RGB source.

FIG. 1(c) illustrates a 16×9 format display ratio main signal in which a4×3 format display ratio inset picture is displayed. If both the mainand auxiliary video signals are 16×9 format display ratio sources, theinset picture can also have a 16×9 format display ratio. The insetpicture can be displayed in many different positions.

FIG. 1(d) illustrates a display format, wherein the main and auxiliaryvideo signals are displayed with the same size picture. Each displayarea has an format display ratio of 8×9, which is of course differentfrom both 16×9 and 4×3. In order to show a 4×3 format display ratiosource in such a display area, without horizontal or verticaldistortion, the signal must be cropped on the left and/or right sides.More of the picture can be shown, with less cropping, if some aspectratio distortion by horizontal squeezing of the picture is tolerated.Horizontal squeezing results in vertical elongation of objects in thepicture. The wide screen television according to this invention canprovide any mix of cropping and aspect ratio distortion from maximumcropping with no aspect ratio distortion to no cropping with maximumaspect ratio distortion.

Data sampling limitations in the auxiliary video signal processing pathcomplicate the generation of a high resolution picture which is as largein size as the display from the main video signal. Various methods canbe developed for overcoming these complications.

FIG. 1(e) is a display format wherein a 4×3 format display ratio pictureis displayed in the center of a 16×9 format display ratio screen. Darkbars are evident on the right and left sides.

FIG. 1(f) illustrates a display format wherein one large 4×3 formatdisplay ratio picture and three smaller 4×3 format display ratiopictures are displayed simultaneously. A smaller picture outside theperimeter of the large picture is sometimes referred to as a POP, thatis a picture-outside-picture, rather than a PIP, a picture-in-picture.The terms PIP or picture-in-picture are used herein for both displayformats. In those circumstances where the wide screen television isprovided with two tuners, either both internal or one internal and oneexternal, for example in a video cassette recorder, two of the displayedpictures can display movement in real time in accordance with thesource. The remaining pictures can be displayed in freeze frame format.It will be appreciated that the addition of further tuners andadditional auxiliary signal processing paths can provide for more thantwo moving pictures. It will also be appreciated that the large pictureon the one hand, and the three small pictures on the other hand, can beswitched in position, as shown in FIG. 1(g).

FIG. 1(h) illustrates an alternative wherein the 4×3 format displayratio picture is centered, and six smaller 4×3 format display ratiopictures are displayed in vertical columns on either side. As in thepreviously described format, a wide screen television provided with twotuners can provide two moving pictures. The remaining eleven pictureswill be in freeze frame format.

FIG. 1(i) shows a display format having a grid of twelve 4×3 formatdisplay ratio pictures. Such a display format is particularlyappropriate for a channel selection guide, wherein each picture is atleast a freeze frame from a different channel. As before, the number ofmoving pictures will depend upon the number of available tuners andsignal processing paths.

The various formats shown in FIG. 1 are illustrative, and not limiting,and can be implemented by wide screen televisions shown in the remainingdrawings and described in detail below.

An overall block diagram for a wide screen television in accordance withinventive arrangements, and adapted to operate with 2f_(H) horizontalscanning, is shown in FIG. 2 and generally designated 10. The television10 generally comprises a video signals input section 20, a chassis or TVmicroprocessor 216, a wide screen processor 30, a 1f_(H) to 2f_(H)converter 40, a deflection circuit 50, an RGB interface 60, a YUV to RGBconverter 240, kine drivers 242, direct view of projection tubes 244 anda power supply 70. The grouping of various circuits into differentfunctional blocks is made for purposes of convenience in description,and is not intended as limiting the physical position of such circuitsrelative to one another.

The video signals input section 20 is adapted for receiving a pluralityof composite video signals from different video sources. The videosignals may be selectively switched for display as main and auxiliaryvideo signals. An RF switch 204 has two antenna inputs ANT1 and ANT 2.These represent inputs for both off-air antenna reception and cablereception. The RF switch 204 controls which antenna input is supplied toa first tuner 206 and to a second tuner 208. The output of first tuner206 is an input to a one-chip 202, which performs a number of functionsrelated to tuning, horizontal and vertical deflection and videocontrols. The particular one-chip shown is industry designated typeTA7730. The baseband video signal VIDEO OUT developed in the one-chipand resulting from the signal from first tuner 206 is an input to bothvideo switch 200 and the TV1 input of wide screen processor 30. Otherbaseband video inputs to video switch 200 are designated AUX1 and AUX 2.These might be used for video cameras, laser disc players, video tapeplayers, video games and the like. The output of the video switch 200,which is controlled by the chassis or TV microprocessor 216 isdesignated SWITCHED VIDEO. The SWITCHED VIDEO is another input to widescreen processor 30.

With further reference to FIG. 3, a switch SW1 wide screen processorselects between the TV1 and SWITCHED VIDEO signals as a SEL COMP OUTvideo signal which is an input to a Y/C decoder 210. The Y/C decoder 210may be implemented as an adaptive line comb filter. Two further videosources S1 and S2 are also inputs to the Y/C decoder 210. Each of S1 andS2 represent different S-VHS sources, and each consists of separateluminance and chrominance signals. A switch, which may be incorporatedas part of the Y/C decoder, as in some adaptive line comb filters, orwhich may be implemented as a separate switch, is responsive to the TVmicroprocessor 216 for selecting one pair of luminance and chrominancesignals as outputs designated Y₋₋ M and C₋₋ IN respectively. Theselected pair of luminance and chrominance signals is thereafterconsidered the main signal and is processed along a main signal path.Signal designations including ₋₋ M or ₋₋ MN refer to the main signalpath. The chrominance signal C₋₋ IN is redirected by the wide screenprocessor back to the one-chip, for developing color difference signalsU₋₋ M and V₋₋ M. In this regard, U is an equivalent designation for(R-Y) and V is an equivalent designation for (B-Y). The Y₋₋ M, U₋₋ M,and V₋₋ M signals are converted to digital form in the wide screenprocessor for further signal processing.

The second tuner 208, functionally defined as part of the wide screenprocessor 30, develops a baseband video signal TV2. A switch SW2 selectsbetween the TV2 and SWITCHED VIDEO signals as an input to a Y/C decoder220. The Y/C decoder 220 may be implemented as an adaptive line combfilter. Switches SW3 and SW4 select between the luminance andchrominance outputs of Y/C decoder 220 and the luminance and chrominancesignals of an external video source, designated Y₋₋ EXT and C₋₋ EXTrespectively. The Y₋₋ EXT and C₋₋ EXT signals correspond to the S-VHSinput S1. The Y/C decoder 220 and switches SW3 and SW4 may be combined,as in an adaptive line comb filter. The output of switches SW3 and SW4is thereafter considered the auxiliary signal and is processed along anauxiliary signal path. The selected luminance output is designated Y₋₋A. Signal designations including ₋₋ A, ₋₋ AX and ₋₋ AUX refer to theauxiliary signal path. The selected chrominance is converted to colordifference signals U₋₋ A and V₋₋ A. The Y₋₋ A, U₋₋ A and V₋₋ A signalsare converted to digital form for further signal processing. Thearrangement of video signal source switching in the main and auxiliarysignal paths maximizes flexibility in managing the source selection forthe different parts of the different picture display formats.

A composite synchronizing signal COMP SYNC, corresponding to Y₋₋ M isprovided by the wide screen processor to a sync separator 212. Thehorizontal and vertical synchronizing components H and V respectivelyare inputs to a vertical countdown circuit 214. The vertical countdowncircuit develops a VERTICAL RESET signal which is directed into the widescreen processor 30. The wide screen processor generates an internalvertical reset output signal INT VERT RST OUT directed to the RGBinterface 60. A switch in the RGB interface 60 selects between theinternal vertical reset output signal and the vertical synchronizingcomponent of the external RGB source. The output of this switch is aselected vertical synchronizing component SEL₋₋ VERT₋₋ SYNC directed tothe deflection circuit 50. Horizontal and vertical synchronizing signalsof the auxiliary video signal are developed by sync separator 250 in thewide screen processor.

The 1f_(H) to 2f_(H) converter 40 is responsible for convertinginterlaced video signals to progressively scanned noninterlaced signals,for example one wherein each horizontal line is displayed twice, or anadditional set of horizontal lines is generated by interpolatingadjacent horizontal lines of the same field. In some instances, the useof a previous line or the use of an interpolated line will depend uponthe level of movement which is detected between adjacent fields orframes. The converter circuit 40 operates in conjunction with a videoRAM 420. The video RAM may be used to store one or more fields of aframe, to enable the progressive display. The converted video data asY₋₋ 2f_(H), U₋₋ 2f_(H) and V₋₋ 2f_(H) signals is supplied to the RGBinterface 60.

The RGB interface 60, shown in more detail in FIG. 14, enables selectionof the converted video data or external RGB video data for display bythe video signals input section. The external RGB signal is deemed to bea wide format display ratio signal adapted for 2f_(H) scanning. Thevertical synchronizing component of the main signal is supplied to theRGB interface by the wide screen processor as INT VERT RST OUT, enablinga selected vertical sync (f_(Vm) or f_(Vext)) to be available to thedeflection circuit 50. Operation of the wide screen television enablesuser selection of an external RGB signal, by generating aninternal/external control signal INT/EXT. However, the selection of anexternal RGB signal input, in the absence of such a signal, can resultin vertical collapse of the raster, and damage to the cathode ray tubeor projection tubes. Accordingly, the RGB interface circuit detects anexternal synchronizing signal, in order to override the selection of anon-existent external RGB input. The WSP microprocessor 340 alsosupplies color and tint controls for the external RGB signal.

The wide screen processor 30 comprises a picture in picture processor320 for special signal processing of the auxiliary video signal. Theterm picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. Agate array 300 combines the main and auxiliary video signal data in awide variety of display formats, as shown by the examples of FIGS. 1(b)through 1(i). The picture-in-picture processor 320 and gate array 300are under the control of a wide screen microprocessor (WSP μP) 340.Microprocessor 340 is responsive to the TV microprocessor 216 over aserial bus. The serial bus includes four signal lines, for data, clocksignals, enable signals and reset signals. The wide screen processor 30also generates a composite vertical blanking/reset signal, as a threelevel sandcastle signal. Alternatively, the vertical blanking and resetsignals can be generated as separate signals. A composite blankingsignal is supplied by the video signal input section to the RGBinterface.

The deflection circuit 50, shown in more detail in FIG. 13, receives avertical reset signal from the wide screen processor, a selected 2f_(H)horizontal synchronizing signal from the RGB interface 60 and additionalcontrol signals from the wide screen processor. These additional controlsignals relate to horizontal phasing, vertical size adjustment andeast-west pin adjustment. The deflection circuit 50 supplies 2f_(H)flyback pulses to the wide screen processor 30, the 1f_(H) to 2f_(H)converter 40 and the YUV to RGB converter 240.

Operating voltages for the entire wide screen television are generatedby a power supply 70 which can be energized by an AC mains supply.

The wide screen processor 30 is shown in more detail in FIG. 3. Theprincipal components of the wide screen processor are a gate array 300,a picture-in-picture circuit 301, analog to digital and digital toanalog converters, the second tuner 208, a wide screen processormicroprocessor 340 and a wide screen output encoder 227. Further detailsof the wide screen processor, which are in common with both the 1f_(H)and the 2f_(H) chassis, for example the PIP circuit, are shown in FIG.4. A picture-in-picture processor 320, which forms a significant part ofthe PIP circuit 301, is shown in more detail in FIG. 5. The gate array300 is shown in more detail in FIG. 6. A number of the components shownin FIG. 3, forming parts of the main and auxiliary signal paths, havealready been described in detail.

The second tuner 208 has associated therewith an IF stage 224 and anaudio stage 226. The second tuner 208 also operates in conjunction withthe WSP μP 340. The WSP μP 340 comprises an input output I/O section340A and an analog output section 340B. The I/O section 340A providestint and color control signals, the INT/EXT signal for selecting theexternal RGB video source and control signals for the switches SW1through SW6. The I/O section also monitors the EXT SYNC DET signal fromthe RGB interface to protect the deflection circuit and cathode raytube(s). The analog output section 340B provides control signals forvertical size, eastwest adjust and horizontal phase, through respectiveinterface circuits 254, 256 and 258.

The gate array 300 is responsible for combining video information fromthe main and auxiliary signal paths to implement a composite wide screendisplay, for example one of those shown in the different parts ofFIG. 1. Clock information for the gate array is provided by phase lockedloop 374, which operates in conjunction with low pass filter 376. Themain video signal is supplied to the wide screen processor in analogform, and Y U V format, as signals designated Y₋₋ M, U₋₋ M and V₋₋ M.These main signals are converted from analog to digital form by analogto digital converters 342 and 346, shown in more detail in FIG. 4.

The color component signals are referred to by the generic designationsU and V, which may be assigned to either R-Y or B-Y signals, or I and Qsignals. The sampled luminance bandwidth is limited to 8 MHz because thesystem clock rate is 1024f_(H), which is approximately 16 MHz. A singleanalog to digital converter and an analog switch can be used to samplethe color component data because the U and V signals are limited to 500KHz, or 1.5 MHz for wide I. The select line UV₋₋ MUX for the analogswitch, or multiplexer 344, is an 8 MHz signal derived by dividing thesystem clock by 2. A one clock wide start of line SOL pulsesynchronously resets this signal to zero at the beginning of eachhorizontal video line. The UV₋₋ MUX line than toggles in state eachclock cycle through the horizontal line. Since the line length is aneven number of clock cycles, the state of the UV₋₋ MUX, onceinitialized, will consistently toggle 0, 1, 0, 1, . . . , withoutinterruption. The Y and UV data streams out of the analog to digitalconverters 342 and 346 are shifted because the analog to digitalconverters each have 1 clock cycle of delay. In order to accommodate forthis data shift, the clock gating information from the interpolatorcontrol 349 of main signal processing path 304 must be similarlydelayed. Were the clock gating information not delayed, the UV data willnot be correctly paired when deleted. This is important because each UVpair represents one vector. A U element from one vector cannot be pairedwith a V element from another vector without causing a color shift.Instead, a V sample from a previous pair will be deleted along with thecurrent U sample. This method of UV multiplexing is referred to as2:1:1, as there are two luminance samples for every pair of colorcomponent (U, V) samples. The Nyquist frequency for both U and V iseffectively reduced to one half of the luminance Nyquist frequency.Accordingly, the Nyquist frequency of the output of the analog todigital converter for the luminance component is 8 MHz, whereas theNyquist frequency of the output of the analog to digital converter forthe color components is 4 MHz.

The PIP circuit and/or the gate array may also include means forenhancing the resolution of the auxiliary data notwithstanding the datacompression. A number of data reduction and data restoration schemeshave been developed, including for example paired pixel compression anddithering and dedithering. Moreover, different dithering sequencesinvolving different numbers of bits and different paired pixelcompressions involving different numbers of bits are contemplated. Oneof a number of particular data reduction and restoration schemes can beselected by the WSP μP 340 in order to maximize resolution of thedisplayed video for each particular kind of picture display format.

The gate array includes interpolators which operate in conjunction withline memories, which may be implemented as FIFO's 356 and 358. Theinterpolator and FIFO's are utilized to resample the main signal asdesired. An additional interpolator can resample the auxiliary signal.Clock and synchronizing circuits in the gate array control the datamanipulation of both the main and auxiliary signals, including thecombination thereof into a single output video signal having Y₋₋ MX, U₋₋MX and V_(--MX) components. These output components are converted toanalog form by digital to analog converters 360, 362 and 364. The analogform signals, designated Y, U and V, are supplied to the 1f_(H) to2f_(H) converter 40 for conversion to noninterlaced scanning. The Y, Uand V signals are also encoded to Y/C format by encoder 227 to define awide format ratio output signal Y₋₋ OUT₋₋ EXT/C₋₋ OUT₋₋ EXT available atpanel jacks. Switch SW5 selects a synchronizing signal for the encoder227 from either the gate array, C₋₋ SYNC₋₋ MN, or from the PIP circuit,C₋₋ SYNC₋₋ AUX. Switch SW6 selects between Y₋₋ M and C₋₋ SYNC₋₋ AUX assynchronizing signal for the wide screen panel output.

Portions of the horizontal synchronizing circuit are shown in moredetail in FIG. 12. Phase comparator 228 is part of a phase locked loopincluding low pass filter 230, voltage controlled oscillator 232,divider 234 and capacitor 236. The voltage controlled oscillator 232operates at 32f_(H), responsive to a ceramic resonator or the like 238.The output of the voltage controlled oscillator is divided by 32 toprovide a proper frequency second input signal to phase comparator 228.The output of the divider 234 is a 1f_(H) REF timing signal. The 32f_(H)REF and 1f_(H) REF timing signals are supplied to a divide by 16 counter400. A 2f_(H) output is supplied to a pulse width circuit 402.Presetting divider 400 by the 1f_(H) REF signal assures that the divideroperates synchronously with the phase locked loop of the video signalsinput section. Pulse width circuit 402 assures that a 2f_(H) -REF signalwill have an adequate pulse width to assure proper operation of thephase comparator 404. for example a type CA1391, which forms part of asecond phase locked loop including low pass filter 406 and 2f_(H)voltage controlled oscillator 408. Voltage controlled oscillator 408generates an internal 2f_(H) timing signal, which is used for drivingthe progressively scanned display. The other input signal to phasecomparator 404 is the 2f_(H) flyback pulses or a timing signal relatedthereto. The use of the second phase locked loop including phasecomparator 404 is useful for assuring that each 2f_(H) scanning periodis symmetric within each 1f_(H) period of the input signal. Otherwise,the display may exhibit a raster split, for example, wherein half of thevideo lines are shifted to the right and half of the video lines areshifted to the left.

The deflection circuit 50 is shown in more detail in FIG. 13. A circuit500 is provided for adjusting the vertical size of the raster, inaccordance with a desired amount of vertical overscan necessary forimplementing different display formats. As illustrated diagrammatically,a constant current source 502 provides a constant quantity of currentI_(RAMP) which charges a vertical ramp capacitor 504. A transistor 506is coupled in parallel with the vertical ramp capacitor, andperiodically discharges the capacitor responsive to the vertical resetsignal. In the absence of any adjustment, current I_(RAMP) provides themaximum available vertical size for the raster. This might correspond tothe extent of vertical overscan needed to fill the wide screen displayby an expanded 4×3 format display ratio signal source, as shown in FIG.1(a). To the extent that less vertical raster size is required, anadjustable current source 508 diverts a variable amount of currentI_(ADJ) from I_(RAMP), so that vertical ramp capacitor 504 charges moreslowly and to a smaller peak value. Variable current source 508 isresponsive to a vertical size adjust signal, for example in analog form,generated by a vertical size control circuit. Vertical size adjustment500 is independent of a manual vertical size adjustment 510, which maybe implemented by a potentiometer or back panel adjustment knob. Ineither event, the vertical deflection coil(s) 512 receive(s) drivingcurrent of the proper magnitude. Horizontal deflection is provided byphase adjusting circuit 518, East-West pin correction circuit 514, a2f_(H) phase locked loop 520 and horizontal output circuit 516.

The RGB interface circuit 60 is shown in more detailed in FIG. 14. Thesignal which is to be ultimately displayed will be selected between theoutput of the 1f_(H) to 2f_(H) converter 40 and an external RGB input.For purposes of the wide screen television described herein, theexternal RGB input is presumed to be a wide format display ratio,progressively scanned source. The external RGB signals and a compositeblanking signal from the video signals input section 20 are inputs to anRGB to Y U V converter 610. The external 2f_(H) composite synchronizingsignal for the external RGB signal is an input to external synchronizingsignal separator 600. Selection of the vertical synchronizing signal isimplemented by switch 608. Selection of the horizontal synchronizingsignal is implemented by switch 604. Selection of the video signal isimplemented by switch 606. Each of the switches 604, 606 and 608 isresponsive to an internal/external control signal generated by the WSPμP 340. Selection of internal or external video sources is a userselection. However, if a user inadvertently selects an external RGBsource, when no such source is connected or turned on, or if theexternal source drops out, the vertical raster will collapse, andserious damage to the cathode ray tube(s) can result. Accordingly, anexternal synchronizing detector 602 checks for the presence of anexternal synchronizing signal. In the absence of such a signal, a switchoverride control signal is transmitted to each of switches 604, 606 and608, to prevent selection of the external RGB source if the signaltherefrom is not present. The RGB to YUV converter 610 also receivestint and color control signals from the WSP μP 340.

A wide screen television in accordance with the inventive arrangementscan be implemented with 1f_(H) horizontal scanning instead of 2f_(H)horizontal scanning, although such a circuit is not illustrated. A1f_(H) circuit would not require the 1f_(H) to 2f_(H) converter and theRGB interface. Accordingly, there would be no provision for displayingan external wide format display ratio RGB signal at a 2f_(H) scanningrate. The wide screen processor and picture-in-picture processor for a1f_(H) circuit would be very similar. The gate array could besubstantially identical, although not all of the inputs and outputswould be utilized. The various resolution enhancement schemes describedherein can be generally applied without regard to whether the televisionoperates with 1f_(H) or 2f_(H) scanning.

FIG. 4 is a block diagram showing further details of the wide screenprocessors 30 shown in FIG. 3 which would be the same for both a 1f_(H)and 2f_(H) chassis. The Y₋₋ A, U₋₋ A and V₋₋ A signals are an input tothe picture in picture processor 320, which can include a resolutionprocessing circuit 370. The wide screen television according to aspectsof this invention can expand and compress video. The special effectsembodied by the various composite display formats illustrated in part inFIG. 1 are generated by the picture-in-picture processor 320, which canreceive resolution processed data signals Y₋₋ RP, U₋₋ RP and V₋₋ RP fromresolution processing circuit 370. Resolution processing need not beutilized at all times, but during selected display formats. Thepicture-in-picture processor 320 is shown in more detail in FIG. 5. Theprincipal components of the picture-in-picture processor are ananalog-to-digital converter section 322, an input section 324, a fastswitch (FSW) and bus section 326, a timing and control section 328 and adigital-to-analog converter section 330. The timing and control section328 is shown in more detail in FIG. 11.

The picture-in-picture processor 320 may be embodied as an improvedvariation of a basic CPIP chip developed by Thomson ConsumerElectronics, Inc. The basic CPIP chip is described more fully in apublication entitled The CTC 140 Picture in Picture (CPIP) TechnicalTraining Manual, available from Thomson Consumer Electronics, Inc.,Indianapolis, Ind. A number of special features or special effects arepossible, the following being illustrative. The basic special effect isa large picture having a small picture overlaying a portion thereof asshown in FIG. 1(c). The large and small pictures can result from thesame video signal, from different video signals and can be interchangedor swapped. Generally speaking, the audio signal is switched to alwayscorrespond to the big picture. The small picture can be moved to anyposition on the screen or can step through a number of predeterminedpositions. A zoom feature increases and decreases the size of the smallpicture, for example to any one of a number of preset sizes. At somepoint, for example the display format shown in FIG. 1(d), the large andsmall pictures are in fact the same size.

In a single picture mode, for example that shown in FIGS. 1(b), 1(e) or1(f) a user can zoom in on the content of the single picture, forexample, in steps from a ratio of 1.0:1 to 5.0:1. While in the zoom modea user may search or pan through the picture content enabling the screenimage to move across different areas of the picture. In either event,either the small picture or the large picture or the zoomed picture canbe displayed in freeze frame (still picture format). This functionenables a strobe format, wherein the last nine frames of video can berepeated on the screen. The frame repetition rate can be changed fromthirty frames per second to zero frames per second.

The picture-in-picture processor used in the wide screen televisionaccording to another inventive arrangement differs from the presentconfiguration of the basic CPIP chip itself as described above. If thebasic CPIP chip were used with a television having a 16×9 screen, andwithout a video speed up circuit, the inset pictures would exhibitaspect ratio distortion, due to the effective 4/3 times horizontalexpansion resulting from scanning across the wider 16×9 screen. Objectsin the picture would be horizontally elongated. If an external speed upcircuit were utilized, there would be no aspect ratio distortion, butthe picture would not fill the entire screen.

Existing picture-in-picture processors based on the basic CPIP chip asused in conventional televisions are operated in a particular fashionhaving certain undesirable consequences. The incoming video is sampledwith a 640f_(H) clock which is locked to the horizontal synchronizingsignal of the main video source. In other words, data stored in thevideo RAM associated with the CPIP chip is not orthogonally sampled withrespect to the incoming auxiliary video source. This is a fundamentallimitation on the basic CPIP method of field synchronization. Thenonorthogonal nature of the input sampling rate results in skew errorsof the sampled data. The limitation is a result of the video RAM usedwith the CPIP chip, which must use the same clock for writing andreading data. When data from the video RAM, such as video RAM 350, isdisplayed, the skew errors are seen as random jitter along verticaledges of the picture and are generally considered quite objectionable.

The picture-in-picture processor 320, according to an inventivearrangement and unlike the basic CPIP chip, is adapted forasymmetrically compressing the video data in one of a plurality ofdisplay modes. In this mode of operation, the pictures are compressed4:1 in the horizontal direction and 3:1 in the vertical direction. Thisasymmetric mode of compression produces aspect ratio distorted picturesfor storage in the video RAM. Objects in the pictures are squeezedhorizontally. However, if these pictures are read out normally, as forexample in the channel scan mode, for display of a 16×9 format displayratio screen, the pictures appear correct. The picture fills the screenand there is no aspect ratio distortion. The asymmetric compression modeaccording to this aspect of the invention makes it possible to generatethe special display formats on a 16×9 screen without external speed upcircuitry.

FIG. 11 is a block diagram of the timing and control section 328 of thepicture-in-picture processor, for example a modified version of the CPIPchip described above, which includes a decimation circuit 328C forimplementing the asymmetric compression as one of a plurality ofselectable display modes. The remaining display modes can provideauxiliary pictures of different sizes. Each of horizontal and verticaldecimation circuits comprises a counter which is programmed for acompression factor from a table of values under the control of the WSPμP 340. The range of values can be 1:1, 2:1, 3:1 and so on. Thecompression factors can be symmetric or asymmetric, depending upon howthe table is set up. Control of the compression ratios can also beimplemented by fully programmable, general purpose decimation circuitsunder the control of the WSP μP 340.

In full screen PIP modes, the picture-in-picture processor, inconjunction with a free running oscillator 348 will take Y/C input froma decoder, for example an adaptive line comb filter, decode the signalinto Y, U, V color components and generate horizontal and vertical syncpulses. These signals are processed in the picture-in-picture processorfor the various full screen modes such as zoom, freeze and channel scan.During the channel scan mode, for example, the horizontal and verticalsync present from the video signals input section will have manydiscontinuities because the signals sampled (different channels) willhave non-related sync pulses and will be switched at seemingly randommoments in time. Therefore the sample clock (and read/write video RAMclock) is determined by the free running oscillator. For freeze and zoommodes, the sample clock will be locked to incoming video horizontalsync, which in these special cases is the same as the display clockfrequency.

Referring again to FIG. 4, Y, U, V and C₋₋ SYNC (composite sync) outputsfrom the picture-in-picture processor in analog form can be re-encodedinto Y/C components by encode circuit 366, which operates in conjunctionwith a 3.58 MHz oscillator 380. This Y/C₋₋ PIP₋₋ ENC signal may beconnected to a Y/C switch, not shown, which enables the re-encoded Y/Ccomponents to be substituted for the Y/C components of the main signal.From this point on, the PIP encoded Y, U, V and sync signals would bethe basis for horizontal and vertical timing in the rest of the chassis.This mode of operation is appropriate for implementing a zoom mode forthe PIP, based upon operation of the interpolator and FIFO's in the mainsignal path.

With further reference to FIG. 5, the picture-in-picture processor 320comprises analog to digital converting section 322, input section 324,fast switch FSW and bus control section 326, timing and control section328 and digital to analog converting section 330. In general, thepicture-in-picture processor 320 digitizes the video signal intoluminance (Y) and color difference signals (U, V), subsampling andstoring the results in a 1 megabit video RAM 350 as explained above. Thevideo RAM 350 associated with the picture-in-picture processor 320 has amemory capacity of 1 megabit, which is not large enough to store a fullfield of video data with 8-bit samples. Increased memory capacity tendsto be expensive and can require more complex management circuitry. Thesmaller number of bits per sample in the auxiliary channel represents areduction in quantization resolution, or bandwidth, relative to the mainsignal, which is processed with 8-bit samples throughout. This effectivereduction of bandwidth is not usually a problem when the auxiliarydisplayed picture is relatively small, but can be troublesome if theauxiliary displayed picture is larger, for example the same size as themain displayed picture. Resolution processing circuit 370 canselectively implement one or more schemes for enhancing the quantizationresolution or effective bandwidth of the auxiliary video data. A numberof data reduction and data restoration schemes have been developed,including for example, paired pixel compression and dithering anddedithering. A dedithering circuit would be operatively disposeddownstream of the video RAM 350, for example in the auxiliary signalpath of the gate array, as explained in more detail below. Moreover,different dithering and dedithering sequences involving differentnumbers of bits and different paired pixel compressions involvingdifferent number of bits are contemplated. One of a number of particulardata reduction and restoration schemes can be selected by the WSP μP inorder to maximize resolution of the displayed video for each particularkind of picture display format.

The luminance and color difference signals are stored in an 8:1:1six-bit Y, U, V fashion. In other words, each component is quantizedinto six-bit samples. There are eight luminance samples for every pairof color difference samples. The picture-in-picture processor 320 isoperated in a mode whereby incoming video data is sampled with a640f_(H) clock rate locked to the incoming auxiliary video synchronizingsignal instead. In this mode, data stored in the video RAM isorthogonally sampled. When the data is read out of thepicture-in-picture processor video RAM 350, it is read using the same640f_(H) clock locked to the incoming auxiliary video signal. However,even though this data was orthogonally sampled and stored, and can beread out orthogonally, it cannot be displayed orthogonally directly fromthe video RAM 350, due to the asynchronous nature of the main andauxiliary video sources. The main and auxiliary video sources might beexpected to be synchronous only in that instance where they aredisplaying signals from the same video source.

Further processing is required in order to synchronize the auxiliarychannel, that is the output of data from the video RAM 350, to the mainchannel. With reference again to FIG. 4, two four bit latches 352A and352B are used to recombine the 8-bit data blocks from the video RAM4-bit output port. The four bit latches also reduce the data clock ratefrom 1280f_(H) to 640f_(H).

Generally, the video display and deflection system is synchronized withthe main video signal. The main video signal must be speeded up, asexplained above, to fill the wide screen display. The auxiliary videosignal must be vertically synchronized with the first video signal andthe video display. The auxiliary video signal can be delayed by afraction of a field period in a field memory, and then expanded in aline memory. Synchronization of the auxiliary video data with main videodata is accomplished by utilizing the video RAM 350 as a field memoryand a first in first out (FIFO) line memory device 354 for expanding thesignal. The size of FIFO 354 is 2048×8. The size of FIFO is related tothe minimum line storage capacity thought to be reasonably necessary toavoid read/write pointer collisions. Read/write pointer collisions occurwhen old data is read out of the FIFO before new data has an opportunityto be written into the FIFO. Read/write pointer collisions also occurwhen new data overwrites the memory before the old data has anopportunity to be read out of the FIFO.

The 8-bit DATA₋₋ PIP data blocks from video RAM 350 are written into2048×8 FIFO 354 with the same picture-in-picture processor 640f_(H)clock which was used to sample the video data, that is, the 640f_(H)clock which is locked to the auxiliary signal, rather than the mainsignal. The FIFO 354 is read using the display clock of 1024f_(H), whichis locked to horizontal synchronizing component of the main videochannel. The use of a multiple line memory (FIFO) which has independentread and write port clocks enables data which was orthogonally sampledat a first rate to be displayed orthogonally at a second rate. Theasynchronous nature of the read and write clocks, however, does requirethat steps be undertaken to avoid read/write pointer collisions.

The main signal path 304, auxiliary signal path 306 and output signalpath 312 of the gate array 300 are shown in block diagram form in FIG.6. The gate array also comprises a clocks/sync circuit 320 and a WSP μPdecoder 310. Data and address output lines of the WSP μP decoder 310,identified as WSP DATA, are supplied to each of the main circuits andpaths identified above, as well as to the picture-in-picture processor320 and resolution processing circuit 370. It will be appreciated thatwhether or not certain circuits are, or are not, defined as being partof the gate array is largely a matter of convenience for facilitatingexplanation of the inventive arrangements.

The gate array is responsible for expanding, compressing and croppingvideo data of the main video channel, as and if necessary, to implementdifferent picture display formats. The luminance component Y₋₋ MN isstored in a first in first out (FIFO) line memory 356 for a length oftime depending on the nature of the interpolation of the luminancecomponent. The combined chrominance components U/V₋₋ MN are stored inFIFO 358. Auxiliary signal luminance and chrominance components Y₋₋ PIP,U₋₋ PIP and V₋₋ PIP are developed by demultiplexer 355. The luminancecomponent undergoes resolution processing, as desired, in circuit 357,and is expanded as necessary by interpolator 359, generating signal Y₋₋AUX as an output.

In some instances, the auxiliary display will be as large as the mainsignal display, as shown for example in FIG. 1(d). The memorylimitations associated with the picture-in-picture processor and videoRAM 350 can provide an insufficient number of data points, or pixels forfilling such a large display area. In those circumstances, resolutionprocessing circuit 357 can be used to restore pixels to the auxiliaryvideo signal to replace those lost during data compression, orreduction. The resolution processing may correspond to the resolutionprocessing undertaken by circuit 370 shown in FIG. 4. As an example,circuit 370 may be a dithering circuit and circuit 357 may be adedithering circuit.

The auxiliary video input data is sampled at a 640f_(H) rate and storedin video RAM 350. The auxiliary data is read out of video RAM 350 isdesignated VRAM₋₋ OUT. The PIP circuit 301 also has the capability ofreducing the auxiliary picture by equal integer factors horizontally andvertically, as well as asymmetrically. With further reference to FIG.10, the auxiliary channel data is buffered and synchronized to the mainchannel digital video by the 4 bit latches 352A and 352B, the auxiliaryFIFO 354, timing circuit 369 and synchronization circuit 368. The VRAM₋₋OUT data is sorted into Y (luminance), U, V (color components), andFSW₋₋ DAT (fast switch data) by demultiplexer 355. The FSW₋₋ DATindicates which field type was written into the video RAM. The PIP₋₋ FSWsignal is received directly from the PIP circuit and applied to theoutput control circuit 321 to determine which field read out of videoRAM is to be displayed during the small picture modes.

The auxiliary channel is sampled at 640f_(H) rate while the main channelis sampled at a 1024f_(H) rate. The auxiliary channel FIFO 354 convertsthe data from the auxiliary channel sample rate to the main channelclock rate. In this process, the video signal undergoes an 8/5(1024/640) compression. This is more than the 4/3 compression necessaryto correctly display the auxiliary channel signal. Therefore, theauxiliary channel must be expanded by the interpolator 359 to correctlydisplay a 4×3 small picture. The interpolator 359 is controlled byinterpolator control circuit 371, which is itself responsive to WSP μP340. The amount of interpolator expansion required is 5/6. The expansionfactor X is determined as follows:

    X=(640/1024)*(4/3)=5/6

The chrominance components U₋₋ PIP and V₋₋ PIP are delayed by circuit367 for a length of time depending on the nature of the interpolation ofthe luminance component, generating signals U₋₋ AUX and V₋₋ AUX asoutputs. The respective Y, U and V components of the main and auxiliarysignals are combined in respective multiplexers 315, 317 and 319 in theoutput signal path 312, by controlling the read enable signals of theFIFO's 354, 356 and 358. The multiplexers 315, 317 and 319 areresponsive to output multiplexer control circuit 321. Output multiplexercontrol circuit 321 is responsive to the clock signal CLK, the start ofline signal SOL, the H₋₋ COUNT signal, the vertical blanking resetsignal and the output of the fast switch from the picture-in-pictureprocessor and WSP μP 340. The multiplexed luminance and chrominancecomponents Y₋₋ MX, U₋₋ MX and V₋₋ MX are supplied to respectivedigital/analog converters 360, 362 and 364 respectively. The digital toanalog converters are followed by low pass filters 361, 363 and 365respectively, shown in FIG. 4. The various functions of thepicture-in-picture processor, the gate array and the data reductioncircuit are controlled by WSP μP 340. The WSP μP 340 is responsive tothe TV μP 216, being connected thereto by a serial bus. The serial busmay be a four wire bus as shown, having lines for data, clock signals,enable signals and reset signals. The WSP μP 340 communicates with thedifferent circuits of the gate array through a WSP μP decoder 310.

In one case, it is necessary to compress the 4×3 NTSC video by a factorof 4/3 to avoid aspect ratio distortion of the displayed picture. In theother case, the video can be expanded to perform horizontal zoomingoperations usually accompanied by vertical zooming. Horizontal zoomoperations up to 33% can be accomplished by reducing compressions toless than 4/3. A sample interpolator is used to recalculate the incomingvideo to a new pixel positions because the luminance video bandwidth, upto 5.5 MHz for S-VHS format, occupies a large percentage of the Nyquistfold over frequency, which is 8 MHz for a 1024f_(H) clock.

As shown in FIG. 6, the luminance data Y₋₋ MN is routed through aninterpolator 337 in the main signal path 304 which recalculates samplevalues based on the compression or the expansion of the video. Thefunction of the switches or route selectors 323 and 331 is to reversethe topology of the main signal path 304 with respect to the relativepositions of the FIFO 356 and the interpolator 337. In particular, theseswitches select whether the interpolator 337 precedes the FIFO 356, asrequired for compression, or whether the FIFO 356 precedes theinterpolator 337, as required for expansion. The switches 323 and 331are responsive to a route control circuit 335, which is itselfresponsive to the WSP μP 340. It will be remembered that during smallpicture modes the auxiliary video signal is compressed for storage inthe video RAM 350, and only expansion is necessary for practicalpurposes. Accordingly, no comparable switching is required in theauxiliary signal path.

The main signal path is shown in more detail in FIG. 9. The switch 323is implemented by two multiplexers 325 and 327. Switch 331 isimplemented by multiplexer 333. The three multiplexers are responsive tothe route control circuit 335, which is itself responsive to the WSP μP340. A horizontal timing/synchronization circuit 339 generates timingsignals controlling the writing and reading of the FIFOs, as well aslatches 347 and 351, and multiplexer 353. The clock signal CLK and startof line signal SOL are generated by the clocks/sync circuit 320. Ananalog to digital conversion control circuit 369 is responsive to Y₋₋MN. the WSP μP 340 and the most significant bit of UV₋₋ MN.

An interpolator control circuit 349 generates intermediate pixelposition values (K), interpolator compensation filter weighting (C) andclock gating information CGY for the luminance and CGUV for the colorcomponents. It is the clock gating information which pauses (decimates)or repeats the FIFO data to allow samples not to be written on someclocks for effecting compression or some samples to be read multipletimes for expansion.

Such a compression is illustrated in FIG. 15. The LUMA₋₋ RAMP₋₋ IN linerepresents luminance ramp video data being written into the FIFO. TheWR₋₋ EN₋₋ MN₋₋ Y signal is active high, meaning that when this signal ishigh the data is being written into the FIFO. Every fourth sample isinhibited from being written into the FIFO. The jagged line LUMA₋₋RAMP₋₋ OUT represents the luminance ramp data as it would be read out ofthe FIFO, if the data were not first interpolated. Note that the averageslope of the ramp read out of the luminance FIFO is 33% steeper than theinput ramp. Note also that 33% less active reading time is required toread out the ramp as was required to write in the data. This constitutesthe 4/3 compression. It is the function of the interpolator 337 torecalculate the luminance samples being written into the FIFO so thatthe data read out of the FIFO is smooth, rather than jagged.

Expansions may be performed in exactly the opposite manner ascompressions. In the case of compressions the write enable signal hasclock gating information attached to it in the form of inhibit pulses.For expanding data, the clock gating information is applied to the readenable signal. This will pause the data as it is being read from theFIFO 356, as shown in FIG. 16. The LUMA₋₋ RAMP₋₋ IN line represents thedata prior to being written into the FIFO 356 and the jagged line LUMA₋₋RAMP₋₋ OUT represents the data as it is read out of the FIFO 356. Inthis case it is the function of the interpolator, which follows the FIFO356, to recalculate the sampled data from jagged to smooth after theexpansion. In the expansion case the data must pause while being readfrom the FIFO 356 and while being clocked through the interpolator 337.This is different from the compression case where the data iscontinuously clocked through the interpolator 337. For both cases,compression and expansion, the clock gating operations can easily beperformed in a synchronous manner, that is, events can occur based onthe rising edges of the 1024f_(H) system clock.

There are a number of advantages in this topology for luminanceinterpolation. The clock gating operations, namely data decimation anddata repetition, may be performed in a synchronous manner. If aswitchable video data topology were not used to interchange thepositions of the interpolator and FIFO, the read or write clocks wouldneed to be double clocked to pause or repeat the data. The term doubleclocked means that two data points must be written into the FIFO in asingle clock cycle or read from the FIFO during a single clock cycle.The resulting circuitry cannot be made to operate synchronously with thesystem clock, since the writing or reading clock frequency must be twiceas high as the system clock frequency. Moreover, the switchable topologyrequires only one interpolator and one FIFO to perform both compressionsand expansions. If the video switching arrangement described herein werenot used, the double clocking situation can be avoided only by using twoFIFO's to accomplish the functionality of both compression andexpansion. One FIFO for expansions would need to be placed in front ofthe interpolator and one FIFO for compressions would need to be placedafter the interpolator.

It is difficult to ensure that exactly the same number of samples arewritten into each FIFO as are read out of each FIFO. The clock gatewrite pulses for Y and UV (CGY₋₋ WR and CGUV₋₋ WR) are activesimultaneously, but neither is active at the same time that the clockgate read pulses for Y (CGY₋₋ RD) are active. In other words, adifferent number of clock cycles may be required for the read and writepointers to advance to the same number of places due to the fact thatexpansions and compressions of video data are taking place. A circuitfor ensuring that the same number of samples are written in as are readout is shown in block diagram form in FIG. 17.

FIG. 17 illustrates one of three identical circuits used to generate thewrite and read enable signals for the FIFOs for the Y and UV components,designated WR₋₋ EN₋₋ FIFO₋₋ Y (case 1), WR₋₋ EN₋₋ FIFO₋₋ UV (case 2),RD₋₋ EN₋₋ FIFO₋₋ Y and RD₋₋ EN₋₋ FIFO₋₋ UV. In the case of expansions,the RD₋₋ EN₋₋ FIFO₋₋ Y and RD₋₋ EN₋₋ FIFO₋₋ UV signals prove to beidentical, and may be referred to as RD₋₋ EN₋₋ FIFO₋₋ Y₋₋ UV (case 3).The circuit 1100 is explained first for case 1. Circuit 1100 comparesWR₋₋ BEG₋₋ MN to the upper eight bits of H₋₋ COUNT in comparator 1102.The value H₋₋ COUNT is a ten bit counter value used to determine pixellocation within the line period. The counter is cleared by a start ofline signal SOL. The SOL signal is a single clock wide pulse used toinitialize the horizontal counter H₋₋ COUNT to a value of zero at thebeginning of every line. The SOL pulse is nominally aligned with theleading edge of the horizontal synchronizing component.

The output of comparator 1102 is delayed by circuit 1118 and comparedwith an inverted, but otherwise undelayed version of itself in NAND gate1104. The output of NAND gate 1104, a one clock period wide active LOsignal, is the load LDn input to 10-bit length counter 1106. The LDninput is used to load the 10-bit FIFO length counter 1106 with therising edge of the system clock. The bits of the LENGTH signal areinverted by inverter array 1110. The value LENGTH is used to load theupper eight bits of the ten bit counter to determine the number of datasamples which have actually been written into the FIFO. The output ofthe inverter array 1110 is supplied to the uppermost bits of the load ininput LOAD of counter 1106. The least significant two bits are tiedlogically HI. The effective load in value is ₋₋ LENGTH-1. In order toadjust for the -1 aspect of the ₋₋ LENGTH-1, the counter 1106 is stoppedby the ripple carry out signal RCO, which occurs one clock cycle beforethe length counter 1106 reaches zero. The clock gating information isNORed with the ripple carry out signal RCO in gate 1112. The same enablesignal is inverted by gate 1116 and used as the enable signal for theFIFO. The FIFO memory and the counter are thereby enabled in exactly thesame manner, ensuring the correct number of samples to be written. Incase 2, the WR₋₋ BEG₋₋ MN is also compared to H₋₋ COUNT. However, theCGUV₋₋ WR signal is used to generate the WR₋₋ EN₋₋ FIFO₋₋ UV signal asan output. In case 3, RD₋₋ BEG₋₋ MN is compared to H₋₋ COUNT and theCGY₋₋ RD signal is used to generate the RD₋₋ EN₋₋ FIFO₋₋ Y₋₋ UV signalas an output.

Interpolation of the auxiliary signal takes place in the auxiliarysignal path 306. The PIP circuit 301 manipulates a 6 bit Y, U, V, 8:1:1field memory, video RAM 350, to store incoming video data. The video RAM350 holds two fields of video data in a plurality of memory locations.Each memory location holds eight bits of data. In each 8-bit locationthere is one 6-bit Y (luminance) sample (sampled at 640f_(H)) and 2other bits. These two other bits hold either fast switch data (FSW₋₋DAT) or part of a U or V sample (sampled at 80f_(H)). The FSW₋₋ DATvalues indicate which type type of field was written into video RAM.Since there are two fields of data stored in the video RAM 350, and theentire video RAM 350 is read during the display period, both fields areread during the display scan. The PIP circuit 301 will determine whichfield will be read out of the memory to be displayed through the use ofthe fast switch data. The PIP circuit always reads the opposite fieldtype that is being written to overcome a motion tear problem. If thefield type being read is the opposite type than that being displayed,then the even field stored in the video RAM is inverted by deleting thetop line of the field when the field is read out of memory. The resultis that the small picture maintains correct interlace without a motiontear.

The clocks/syn circuit 320 generates read, write and enable signalsneeded for operating FIFOs 354, 356 and 358. The FIFOs for the main andauxiliary channels are enabled for writing data into storage for thoseportions of each video line which is required for subsequent display.Data is written from one of the main or auxiliary channels, but notboth, as necessary to combine data from each source on the same videoline or lines of the display. The FIFO 354 of the auxiliary channel iswritten synchronously with the auxiliary video signal, but is read outof memory synchronously with the main video signal. The main videosignal components are read into the FIFOs 356 and 358 synchronously withthe main video signal, and are read out of memory synchronously with themain video. How often the read function is switched back and forthbetween the main and auxiliary channels is a function of the particularspecial effect chosen.

Generation of different special effects such as cropped side-by-sidepictures are accomplished through manipulating the read and write enablecontrol signals for the line memory FIFOs. The process for this displayformat is illustrated in FIGS. 7 and 8. In the case of croppedside-by-side displayed pictures, the write enable control signal (WR₋₋EN₋₋ AX) for 2048×8 FIFO 354 of the auxiliary channel is active for(1/2)*(5/12)=5/12 or approximately 41% of the display active line period(post speed up), or 67% of the auxiliary channel active line period (prespeed up), as shown in FIG. 7. This corresponds to approximately 33%cropping (approximately 67% active picture) and the interpolatorexpansion of the signal by 5/6. In the main video channel, shown in theupper part of FIG. 8, the write enable control signal (WR₋₋ EN₋₋ MN₋₋ Y)for the 910×8 FIFOs 356 and 358 is active for (1/2)*(4/3)=0.67 or 67% ofthe display active line period. This corresponds to approximately 33%cropping and a compression ratio of 4/3 being performed on the mainchannel video by the 910×8 FIFOs.

In each of the FIFOs, the video data is buffered to be read out at aparticular point in time. The active region of time where the data maybe read out from each FIFO is determined by the display format chosen.In the example of the side-by-side cropped mode shown, the main channelvideo is being displayed on the left hand half of the display and theauxiliary channel video is displayed on the right hand half of thedisplay. The arbitrary video portions of the waveforms are different forthe main and auxiliary channels as illustrated. The read enable controlsignal (RD₋₋ EN₋₋ MN) of the main channel 910×8 FIFOs is active for 50%of the display active line period of the display beginning with thestart of active video, immediately following the video back porch. Theauxiliary channel read enable control signal (RD₋₋ EN₋₋ AX) is activefor the other 50% of the display active line period beginning with thefalling edge of the RD₋₋ EN₋₋ MN signal and ending with the beginning ofthe main channel video front porch. It may be noted that write enablecontrol signals are synchronous with their respective FIFO input data(main or auxiliary) while the read enable control signals aresynchronous with the main channel video.

The display format shown in FIG. 1(d) is particularly desirable as itenables two nearly full field pictures to displayed in a side by sideformat. The display is particularly effective and appropriate for a wideformat display ratio display, for example 16×9. Most NTSC signals arerepresented in a 4×3 format, which of course corresponds to 12×9. Two4×3 format display ratio NTSC pictures may be presented on the same 16×9format display ratio display, either by cropping the pictures by 33% orsqueezing the pictures by 33%, and introducing aspect ratio distortion.Depending on user preference, the ratio of picture cropping to aspectratio distortion may be set any where in between the limits of 0% and33%. As an example, two side by side pictures may be presented as 16.7%squeezed and 16.7% cropped.

The horizontal display time for a 16×9 format display ratio display isthe same as a 4×3 format display ratio display, because both have 62.5microsecond nominal line length. Accordingly, an NTSC video signal mustbe sped up by a factor of 4/3 to preserve a correct aspect ratio,without distortion. The 4/3 factor is calculated as ratio of the twodisplay formats:

    4/3=(16/9)/(4/3)

Variable interpolators are utilized in accordance with aspects of thisinvention to speed up the video signals. In the past, FIFOs havingdifferent clock rates at the inputs and outputs have been used toperform a similar function. By way of comparison, if two NTSC 4×3 formatdisplay ratio signals are displayed on a single 4×3 format display ratiodisplay, each picture must be distorted or cropped, or some combinationthereof, by 50%. A speed up comparable to that needed for a wide screenapplication is unnecessary.

We claim:
 1. A video signal processing circuit, comprising:a line memoryfor said video signal; means for writing and reading of video datasamples into and out of said line memory, different numbers of datasamples per line being stored during expansion and compression of saidvideo signal; means for comparing a first value, specifying a firstpixel location in the horizontal line period where reading or writing ofsaid line memory is to begin, with a second value specifying a secondpixel location within each line period; means for storing a third valuecorresponding to the number of data samples stored in said line memory;and, means for counting the number of data samples which have actuallybeen written into said line memory or read from said line memory, saidcounting means having an output of said comparing means as a first inputand said third value as a second input.
 2. The circuit of claim 1,further comprising means for smoothing data compressed or expanded insaid line memory.
 3. The circuit of claim 1, wherein said line memory isa first in first out (FIFO) device having independently enabled writeand read ports.
 4. A controller for a line memory in a video signalprocessing circuit, the controller comprising:means for writing andreading of video data samples into and out of said line memory,different numbers of data samples per line being stored during expansionand compression of said video signal; means for comparing a first value,specifying a first pixel location in the horizontal line period wherereading or writing of said line memory is to begin, with a second valuespecifying a second pixel location within each line period; means forstoring a third value corresponding to the number of data samples storedin said line memory; and, means for counting the number of data sampleswhich have actually been written into said line memory or read from saidline memory, said counting means having an output of said comparingmeans as a first input and said third value as a second input.
 5. Thecontroller of claim 4, further comprising means for smoothing datacompressed or expanded in said line memory.
 6. The circuit of claim 4,wherein said line memory is a first in first out (FIFO) device havingindependently enabled write and read ports.